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數字設計和計算機體系結構 RISC-V版(英文版) 版權信息
- ISBN：9787111772569
- 條形碼：9787111772569 ; 978-7-111-77256-9
- 裝幀：平裝-膠訂
- 冊數：暫無
- 重量：暫無
- 所屬分類：>
數字設計和計算機體系結構 RISC-V版(英文版) 本書特色
繼MIPS版和ARM版之后，本書與時俱進地推出了RISC-V版。本書從計算機體系結構的角度，由*基礎的二進制數開始，系統介紹數字邏輯設計的基礎知識，引導讀者逐步了解RISC-V微處理器的設計，并在硬件仿真、軟件仿真和真實硬件中對其進行編程。
數字設計和計算機體系結構 RISC-V版(英文版) 內容簡介
繼MIPS版和ARM版之后，本書與時俱進地推出了RISC-V版，將其作為核心處理器來介紹計算機體系結構的基本概念，涵蓋數字邏輯設計的主要內容，并通過RISC-V處理器的設計強化數字邏輯的概念。書中采用一種獨特的現代數字設計方法，先介紹數字邏輯門，接著講述組合電路和時序電路的設計，并以這些基本的數字邏輯設計概念為基礎，重點介紹如何設計實際的處理器。本書不僅反映了當前數字電路設計的主流方法，而且突出了計算機體系結構的工程特點。此外，大量示例及習題也可以加強讀者對概念和技術的理解。本書適合高等院校計算機相關專業的學生閱讀，也適合從事處理器設計的技術人員參考。
數字設計和計算機體系結構 RISC-V版(英文版)數字設計和計算機體系結構 RISC-V版(英文版) 前言
Preface
This book is unique in its treatment in that it presents digital logic design from the perspective of computer architecture, starting at the beginning with 1’s and 0’s and leading through to the design of a microprocessor.
We believe that building a microprocessor is a special rite of passage for engineering and computer science students. The inner workings of a processor seem almost magical to the uninitiated yet prove to be straightforward when carefully explained. Digital design in and of itself is a powerful and exciting subject. Assembly language programming unveils the inner language spoken by the processor. Microarchitecture is the link that brings it alltogether.
數字設計和計算機體系結構 RISC-V版(英文版) 目錄
Contents
Preface iv
About the Authors x
Chapter 1 From Zero to One 1
1.1 The Game Plan 1
1.2 The Art of Managing Complexity 2
1.2.1 Abstraction 2
1.2.2 Discipline 3
1.2.3 The Three -Y’s 4
1.3 The Digital Abstraction 5
1.4 Number Systems 7
1.4.1 Decimal Numbers 7
1.4.2 Binary Numbers 7
1.4.3 Hexadecimal Numbers 9
1.4.4 Bytes, Nibbles, and All That Jazz 11
1.4.5 Binary Addition 12
1.4.6 Signed Binary Numbers 13
1.5 Logic Gates 17
1.5.1 NOT Gate 18
1.5.2 Buffer 18
1.5.3 AND Gate 18
1.5.4 OR Gate 19
1.5.5 Other Two-Input Gates 19
1.5.6 Multiple-Input Gates 19
1.6 Beneath the Digital Abstraction 20
1.6.1 Supply Voltage 20
1.6.2 Logic Levels 20
1.6.3 Noise Margins 21
1.6.4 DC Transfer Characteristics 22
1.6.5 The Static Discipline 22
1.7 CMOS Transistors 24
1.7.1 Semiconductors 25
1.7.2 Diodes 25
1.7.3 Capacitors 26
1.7.4 nMOS and pMOS Transistors 26
1.7.5 CMOS NOT Gate 29
1.7.6 Other CMOS Logic Gates 29
1.7.7 Transmission Gates 31
1.7.8 Pseudo-nMOS Logic 31
1.8 Power Consumption 32
1.9 Summary and a Look Ahead 34
Exercises 36
Interview Questions 50
Chapter 2 Combinational Logic Design 53
2.1 Introduction 53
2.2 Boolean Equations 56
2.2.1 Terminology 56
2.2.2 Sum-of-Products Form 56
2.2.3 Product-of-Sums Form 58
2.3 Boolean Algebra 58
2.3.1 Axioms 59
2.3.2 Theorems of One Variable 59
2.3.3 Theorems of Several Variables 60
2.3.4 The Truth Behind It All 62
2.3.5 Simplifying Equations 63
2.4 From Logic to Gates 64
2.5 Multilevel Combinational Logic 67
2.5.1 Hardware Reduction 68
2.5.2 Bubble Pushing 69
2.6 X’s and Z’s, Oh My 71
2.6.1 Illegal Value: X 71
2.6.2 Floating Value: Z 72
2.7 Karnaugh Maps 73
2.7.1 Circular Thinking 74
2.7.2 Logic Minimization with K-Maps 75
2.7.3 Don’t Cares 79
2.7.4 The Big Picture 80
2.8 Combinational Building Blocks 81
2.8.1 Multiplexers 81
2.8.2 Decoders 84
2.9 Timing 86
2.9.1 Propagation and Contamination Delay 86
2.9.2 Glitches 90
2.10 Summary 93
Exercises 95
Interview Questions 104
Chapter 3 sequential Logic Design 107
3.1 Introduction 107
3.2 Latches and Flip-Flops 107
3.2.1 SR Latch 109
3.2.2 D Latch 111
3.2.3 D FIip-Flop 112
3.2.4 Register 112
3.2.5 Enabled Flip-Flop 113
3.2.6 Resettable Flip-Flop 114
3.2.7 Transistor-Level Latch and Flip-Flop
Designs 114
3.2.8 Putting It All Together 116
3.3 Synchronous Logic Design 117
3.3.1 Some Problematic Circuits 117
3.3.2 Synchronous Sequential Circuits 118
3.3.3 Synchronous and Asynchronous
Circuits 120
3.4 Finite State Machines 121
3.4.1 FSM Design Example 121
3.4.2 State Encodings 127
3.4.3 Moore and Mealy Machines 130
3.4.4 Factoring State Machines 132
3.4.5 Deriving an FSM from a Schematic 135
3.4.6 FSM Review 138
3.5 Timing of Sequential Logic 139
3.5.1 The Dynamic Discipline 140
3.5.2 System Timing 140
3.5.3 Clock Skew 146
3.5.4 Metastability 149
3.5.5 Synchronizers 150
3.5.6 Derivation of Resolution Time 152
3.6 Parallelism 155
3.7 Summary 159
Exercises 160
Int
Preface iv
About the Authors x
Chapter 1 From Zero to One 1
1.1 The Game Plan 1
1.2 The Art of Managing Complexity 2
1.2.1 Abstraction 2
1.2.2 Discipline 3
1.2.3 The Three -Y’s 4
1.3 The Digital Abstraction 5
1.4 Number Systems 7
1.4.1 Decimal Numbers 7
1.4.2 Binary Numbers 7
1.4.3 Hexadecimal Numbers 9
1.4.4 Bytes, Nibbles, and All That Jazz 11
1.4.5 Binary Addition 12
1.4.6 Signed Binary Numbers 13
1.5 Logic Gates 17
1.5.1 NOT Gate 18
1.5.2 Buffer 18
1.5.3 AND Gate 18
1.5.4 OR Gate 19
1.5.5 Other Two-Input Gates 19
1.5.6 Multiple-Input Gates 19
1.6 Beneath the Digital Abstraction 20
1.6.1 Supply Voltage 20
1.6.2 Logic Levels 20
1.6.3 Noise Margins 21
1.6.4 DC Transfer Characteristics 22
1.6.5 The Static Discipline 22
1.7 CMOS Transistors 24
1.7.1 Semiconductors 25
1.7.2 Diodes 25
1.7.3 Capacitors 26
1.7.4 nMOS and pMOS Transistors 26
1.7.5 CMOS NOT Gate 29
1.7.6 Other CMOS Logic Gates 29
1.7.7 Transmission Gates 31
1.7.8 Pseudo-nMOS Logic 31
1.8 Power Consumption 32
1.9 Summary and a Look Ahead 34
Exercises 36
Interview Questions 50
Chapter 2 Combinational Logic Design 53
2.1 Introduction 53
2.2 Boolean Equations 56
2.2.1 Terminology 56
2.2.2 Sum-of-Products Form 56
2.2.3 Product-of-Sums Form 58
2.3 Boolean Algebra 58
2.3.1 Axioms 59
2.3.2 Theorems of One Variable 59
2.3.3 Theorems of Several Variables 60
2.3.4 The Truth Behind It All 62
2.3.5 Simplifying Equations 63
2.4 From Logic to Gates 64
2.5 Multilevel Combinational Logic 67
2.5.1 Hardware Reduction 68
2.5.2 Bubble Pushing 69
2.6 X’s and Z’s, Oh My 71
2.6.1 Illegal Value: X 71
2.6.2 Floating Value: Z 72
2.7 Karnaugh Maps 73
2.7.1 Circular Thinking 74
2.7.2 Logic Minimization with K-Maps 75
2.7.3 Don’t Cares 79
2.7.4 The Big Picture 80
2.8 Combinational Building Blocks 81
2.8.1 Multiplexers 81
2.8.2 Decoders 84
2.9 Timing 86
2.9.1 Propagation and Contamination Delay 86
2.9.2 Glitches 90
2.10 Summary 93
Exercises 95
Interview Questions 104
Chapter 3 sequential Logic Design 107
3.1 Introduction 107
3.2 Latches and Flip-Flops 107
3.2.1 SR Latch 109
3.2.2 D Latch 111
3.2.3 D FIip-Flop 112
3.2.4 Register 112
3.2.5 Enabled Flip-Flop 113
3.2.6 Resettable Flip-Flop 114
3.2.7 Transistor-Level Latch and Flip-Flop
Designs 114
3.2.8 Putting It All Together 116
3.3 Synchronous Logic Design 117
3.3.1 Some Problematic Circuits 117
3.3.2 Synchronous Sequential Circuits 118
3.3.3 Synchronous and Asynchronous
Circuits 120
3.4 Finite State Machines 121
3.4.1 FSM Design Example 121
3.4.2 State Encodings 127
3.4.3 Moore and Mealy Machines 130
3.4.4 Factoring State Machines 132
3.4.5 Deriving an FSM from a Schematic 135
3.4.6 FSM Review 138
3.5 Timing of Sequential Logic 139
3.5.1 The Dynamic Discipline 140
3.5.2 System Timing 140
3.5.3 Clock Skew 146
3.5.4 Metastability 149
3.5.5 Synchronizers 150
3.5.6 Derivation of Resolution Time 152
3.6 Parallelism 155
3.7 Summary 159
Exercises 160
Int
展開全部
數字設計和計算機體系結構 RISC-V版(英文版) 作者簡介
莎拉·L. 哈里斯（Sarah L. Harris）
內華達大學拉斯維加斯分校電氣與計算機工程系教授。曾在惠普、圣地亞哥超級計算機中心和NVIDIA工作。研究領域包括仿生假肢設計和在硬件中部署機器學習算法。她擁有斯坦福大學電氣工程博士學位。
戴維·哈里斯（David Harris）
哈維·穆德學院工程系教授。曾在英特爾公司從事Itanium和Pentium II處理器的邏輯和電路設計，并曾擔任Broadcom、Sun Microsystems、惠普、Evans & Sutherland等設計公司的顧問，獲得了十余項專利。他擁有斯坦福大學電氣工程博士學位。
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